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PRELIMINARY
* PERFORMANCE (1.8 GHz) 40 dBm Output Power (P1dB) 11 dB Power Gain (G1dB) -44 dBc WCDMA ACPR at 30 dBm output power 180 to 300 mA typical quiescent current (IDQ) 55% Power-Added Efficiency Evaluation Boards Available Additional Design Data Available on Website Usable Gain to 3.8GHz DESCRIPTION AND APPLICATIONS
FPD10000AF
10W PACKAGED POWER PHEMT
SEE PACKAGE OUTLINE FOR MARKING CODE
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The FPD10000AF is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), optimized for power applications in L-Band. The high power flangemount package has been optimized for low electrical parasitics and optimal heatsinking. Typical applications include drivers or output stages in PCS/Cellular base station transmitter amplifiers, as well as other power applications in WLL/WLAN amplifiers. * ELECTRICAL SPECIFICATIONS AT 22C
Parameter Power at 1dB Gain Compression Class B Operation Power Gain at dB Gain Compression Maximum Stable Gain: S21/S12 PIN = 0dBm, 50 system Power-Added Efficiency at 1dB Gain Compression Adjacent Channel Power Ratio WCDMA BTS Forward (64 channels) 10.15 dB Pk/Avg 0.001% Saturated Drain-Source Current Gate-Source Leakage Current Pinch-Off Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (channel-to-case) IDSS IGSO |VP| |VBDGD| CC VDS = 3.0 V; VGS = 0 V VGS = -3 V VDS = 3.0 V; IDS = 19 mA IGD = 19 mA See Note on following page 30 5.2 3 1.1 35 3.5 A mA V V C/W ACPR PAE G1dB MSG VDS = 12V; IDQ = 180 mA VDS = 12V; IDQ = 300 mA VDS = 12 V; IDQ = 180 mA VDS = 12 V; IDQ = 300 mA VDS = 12V; IDQ = 180 mA IRF (drive-up current) ~ 1.5A VDS = 12V; IDQ = 180 mA Channel power = 30 dBm -44 dBc 10 11 16.5 18.0 55 % dB dB Symbol P1dB Test Conditions VDS = 12V; IDQ = 180 mA Min Typ 40 Max Units dBm RF SPECIFICATIONS MEASURED AT f = 1.8 GHz USING CW SIGNAL
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 12/07/04 Email: sales@filcsi.com
PRELIMINARY
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FPD10000AF
10W PACKAGED POWER PHEMT
RECOMMENDED OPERATING BIAS CONDITIONS Drain-Source Voltage: From 10 to 12V Quiescent Current: From 180 (Class B) to 300 mA (Class AB) operation ABSOLUTE MAXIMUM RATINGS1
Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power
2
*
Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp.
3
Test Conditions -3V < VGS < +0V 0V < VDS < +15V For VDS > 2V Forward / Reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions
Min
Max 16 -3 50% IDSS +50/-8 1.75 175
Units V V mA mA W C C W dB %
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression
1
-40
150 42 5
Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes: * Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. * Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Total Power Dissipation to be de-rated as follows above 22C: PTOT= 42 - (0.286W/C) x TPACK where TPACK = source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 55C Source flange temperature: PTOT = 42 - (0.286 x (55 - 22)) = 32.6W * Note on Thermal Resistivity: The nominal value of 3.5C/W is measured with the package mounted on a large heatsink with thermal compound to ensure adequate contact. The package temperature is referred to the Source flange.
*
HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 12/07/04 Email: sales@filcsi.com
PRELIMINARY
FPD10000AF
10W PACKAGED POWER PHEMT
*
BIASING GUIDELINES Dual-bias (separate positive Drain and negative Gate supplies) circuits are recommended, requiring a regulated negative voltage supply for depletion-mode devices such as the FPD10000AF. The Gate bias supply should be capable of sinking / sourcing at least 10mA of current. The bias circuitry must be properly sequenced to ensure that the control Gate voltage (typically -0.6 to -1.0V) is applied to the device before the Drain voltage, otherwise large amounts of Drain-Source current will be drawn, potentially leading to instability and selfoscillation. The recommended 180 - 300 mA bias point is nominally a Class B/AB mode. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point, and significant current drive-up should be expected. If a Class A operation is desired, users should check the de-rating limits given in the previous section to ensure reliable operation.
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PACKAGE OUTLINE (dimensions in millimeters - mm)
PACKAGE MARKING CODE
Example: f1ZD P3F
f = Filtronic 1ZD = Lot and Date Code P2F = Status, Part Code, Part Type Status: D=Development P = Production Part Code denotes model (e.g. FPD10000AF) Part Type: F = FET (pHEMT)
All information and specifications subject to change without notice.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 12/07/04 Email: sales@filcsi.com

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